(a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a transistor of a semiconductor device having a silicide layer and a method of manufacturing the same.
(b) Description of the Related Art
In general, a gate of a transistor in a semiconductor device includes a polysilicon layer. The gate electrode may further include a silicide layer formed on the polysilicon layer for decreasing the resistance of the gate.
Hereinafter, a conventional method of manufacturing a transistor will be described with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, an isolation film 20 is formed in a semiconductor substrate 10 by a Shallow Trench Isolation (STI) process to define an active region. Then, a gate oxide film 30 is formed on an active region of the semiconductor substrate 10, a gate 40 including a polysilicon layer is formed thereon, and an insulating spacer 41 is formed on both side walls of the gate 40. Then, an oxide film 50 is deposited on the entire surface of the substrate 10, and a photoresist pattern 60 is formed on the oxide film 50 by a photolithography process so as to expose a region for forming silicide.
Referring to FIG. 1B, the oxide film 50 exposed by the photoresist pattern 60 is etched by a wet etching process using a wet chemical such as a hydrofluoric acid to expose the region for forming silicide. Here, the region for forming silicide is the upper surface of the gate 40 and a portion of the semiconductor substrate 10 adjacent to the spacer 41.
Then, the photo resist pattern 60 is removed by a well-known method not shown in the drawings, and a silicide layer is selectively formed on the silicide region by a silicidation process to reduce the resistance of the gate 40.
However, during the wet etching process of the oxide film 50, chemicals remain due to the characteristics of the wet etching process, which may especially cause a faster etching process at the interface between films. Therefore, as shown FIG. 1B, a portion ‘A’ in which silicidation has to be prevented is exposed, and the silicide layer is formed on the portion ‘A’. Further, the lateral etching ‘B’ of the gate oxide film 30 under the gate 40 may cause to damage the gate oxide film 30. Electrical properties of the device are deteriorated by the above-mentioned problems, thereby decreasing the yield and the reliability of the device.
Further, only the upper surface of the gate 40 is exposed, such that the supply of silicon atoms from the gate 40 for silicidation is not always as great as might be desired. Accordingly, a desired thickness and range of the silicide layer formed on the upper surface of the gate 40 cannot always be obtained. As a result, it is sometimes difficult to reduce the resistance of the gate 40 to a desired value, such that the pattern shrink of the device is not as effective as might be desired.